Modeling Bias Stress Effect on Threshold Voltage for Amorphous Silicon Thin-Film Transistors and Circuits

In this paper, we study amorphous silicon thin-lmtransistor (TFT) degradation under bias stress effect. To model threshold voltage shift with bias stress effect, fabricated samples are measured for I-V data with bias stress in variations of temperature. Rensselaer Polytechnic Institute (RPI) model is thus adopted to extract model parameters, such as the flat band voltage (VFB), the characteristic voltage for deep states (VO), the conduction band mobility (MUBAND), the channel length modulation parameter (LAMBDA), the power law mobility parameter (GAMMA) and the saturation modulation parameter (ALPHASAT) from the measurement. The model card with those extracted parameters is validated via a TFT circuit simulation. The results of the circuit simulation indicate the relationship of effects depending on the stress and operational temperature.